The present invention relates to an electronic data processing system and more particularly to a memory expansion apparatus for a virtual memory electronic data processing system, as well as, a method for operating the apparatus.
A common problem experienced by users of electronic data processing systems is for the main memory requirement of a given system to grow with time. This common problem stems from the natural tendency of data files used in data bases and/or spreadsheets to grow with time, and the tendency for application programs to grow in size and number as the system evolves. This problem is evidenced by the conventional wisdom for a purchaser to purchase a system that has a memory which may be expanded to at least fifteen per-cent above the maximum memory requirement at the time of purchase. But even when the conventional wisdom is heeded, a user may find a need for expanding system main memory beyond the original maximum memory capacity. Thus, there is a need for the capability to expand the main memory of a system beyond its original maximum capacity.
Further, when the system memory is expanded beyond its original limit, it is highly desirable that any and all application programs, which are currently being used on an unexpanded system, function well on any expanded system. The functioning of the application programs is important from two aspects: cost and performance. If substantial changes need to be made to an application program, expenses will be incurred during a reprogramming. Secondly, the performance of an expanded memory system, in order to be commercially competitive, should be equivalent to or greater than the performance of an unexpanded system.
In a real memory system, where the memory address corresponds to an actual location in read only memory or random access memory, the maximum memory limit usually corresponds to the summation of all addresses below the maximum address accessible by the processor-memory bus. In a system with a sixteen bit processor-memory bus, this maximum would be 65536 when addressing is performed directly in one access cycle. A twenty bit address bus, which is common on most personal computers, would have a maximum of 1,048,576 address locations available directly in one access cycle. This does not mean that these systems cannot have memory capacity greater than that which is addressable in one cycle. In fact, many ways have been devised to expand available memory beyond the maximum memory capacity which is addressable in one access cycle.
It is known to add expanded memory locations, by the addition of either higher capacity memory chips or more memory chips, and to concomitantly add additional parallel address lines to the processor-memory bus in order to address the expanded memory. The known system has a segment register which has segment values of 0 to 15, but as originally supplied the equipment only uses three of the sixteen possible segments to read/write data and instructions into memory. Thus, by adding additional address bus lines and control circuitry, which utilizes the unused and available segment values, the maximum addressable real memory of the known system is expanded from 64 kilobytes (where 1 kilobyte=2.sup.10 or 1024 bytes) to 288 kilobytes. The expansion to the 288 kilobyte real memory capacity of the segment register reached the hardware and software limit. Expansion beyond this limit is not possible without changing the software and incurring a degradation of performance, or changing the processor integrated circuits to ones with larger address buses (which is not economically feasible).
Another known approach for expanding memory capacity beyond the maximum real memory limit is to change the architecture of the system to that of a paged memory system where a page register keeps track of the current page. Paged memory systems typically have one or more banks of real memory with each bank having at least one page, and each page having one or more segments. Expanded addresses are possible because of extra bits which are stored in a page register. But, this type of paging requires the loading of the page register whenever a new page of real memory is used. The loading of the page register takes another write cycle and thereby degrades system performance.
An example of a system which needs to be expanded or extended beyond its original maximum is the NCR System 10000 Model 75. The NCR System 10000 Model 75 system design is generally shown and described in NCR/32 GENERAL INFORMATION MANUAL, published in 1984 by NCR Corporation, Dayton, Ohio, which manual is hereby incorporated by reference. As originally designed, the System 10000 Model 75 has a design maximum of 16 million bytes. This may seem to be a large amount of memory, but this is a 32 bit system, and 16 million bytes is not exceedingly large for such a system. Further, this system stores and retrieves information as four byte words. Thus, this system as originally designed has a maximum of 4 million words. Additionally, the 4 million words may be shared between two dyadic processors, thereby lowering the design maximum memory per processor to 2 million words.
Since the NCR System 10000 is a virtual memory system, performance degrades somewhat when a real memory limit is reached because the virtual operating system must clear an address space in real memory to load the next program from virtual memory by writing the current contents of that address space to virtual memory (i.e. disk memory). This writing of a previous program to disk memory and reading of a current program from disk memory to real memory degrades performance. The more virtual memory writing and reading that takes place between disk and real memory, the lower the performance becomes.
It is therefore an object of the present invention to provide an extended addressable real memory to a virtual system which has already reached its maximum real memory limit.
It is another object of this invention to provide an extended real memory without significantly degrading the operation of the virtual system.
It is a further object of this invention to provide extended real memory in a virtual memory system to prevent performance degradation caused by program transfers between virtual memory and real memory.